The BiTMICRO Blog: Independent Scaling – SSD Dual-ASIC Controller Architecture
The PCIe SSD controller architecture has gone from a multiple-controller to single-controller solution common in enterprise SSDs today.
A multiple-controller architecture was the initial attempt to support PCIe interfaces in SSDs using then-existing SAS/SATA SSD controllers. Inside the drive, a controller that acted as an HBA (Host Bus Adapter) was connected to the SAS/SATA controller. The SAS/SATA controller acted as the flash controller thus effectively pushing the HBA functionality inside the drive. See figure 1.
Figure 1. Multiple-controller architecture with single SAS/SATA controller
To add more room for performance and capacity, the multiple-controller architecture employed a controller that can connect to multiple SAS/SATA controllers. That controller functioned as both an HBA and a RAID controller. This effectively pushed both functionalities (HBA and RAID controllers) inside the drive. See figure 2.
Figure 2. Multiple-controller architecture with RAID controller
However good this seemed, this multiple-controller architecture had the following concerns:
1. High power consumption
2. Greater board real estate
3. High BOM cost
4. Inherited latency issues common to SAS/SATA drives
To address these 4 concerns, chip developers came up with a single-chip SSD controller solution. Inside the drive is a single-chip SSD controller that has the functionalities of an HBA, a RAID controller, and a flash controller. This solution allowed native PCIe interface support, more disk capacity, and higher performance – even in the smaller-form-factor SSDs. See figure 3.
Figure 3. Single-controller architecture
With the adaptation of the single-chip solution, vast improvements were made; however, it still suffers from the following concerns:
1. The drive’s flash channel bandwidth and capacity are limited to the fixed number of flash channels available per SSD controller.
2. The need to support the rapid changes in flash technology may require an expensive re-spin of the SSD controller, thereby shortening its life cycle.
To address these concerns, BiTMICRO developed a solution that combines the features of a single-controller and multiple-controller architecture (without the disadvantages) into its SSD controller with dual-ASIC architecture. BiTMICRO’s dual-ASIC solution divides the SSD controller functionality into two chips. One chip acts as the main controller, while the other chip acts as the flash channel expander. The main controller can be connected to multiple flash channel expander chips. This is illustrated in figure 4.
Figure 4. BiTMICRO’s dual-ASIC architecture
Contrary to the old multiple-controller solutions, the BiTMICRO dual-ASIC solution puts all the intelligence in the main controller. The flash channel expander is a passive chip that handles low-level interface to the flash devices. This approach separates the main controller from the back-end of the SSD controller that is more prone to changes, thereby addressing the problems of a single-chip solution mentioned above.
To increase flash channel bandwidth and capacity, more flash channel expander chips can be instantiated and connected to the main controller. If re-spin is required to support the latest flash channel devices, a less costly re-spin could be done on the flash channel expander chip.
The BiTMICRO dual-ASIC solution addresses the problems of a single-controller solution while also addressing the concerns in a multiple-controller solution. The flash channel expander chip has a relatively small size, lower power consumption, and is cheaper than a SAS/SATA controller. Also, it allowed relatively low power, less board real estate requirement, and a less expensive solution compared to the multiple-controller solution.
Since all intelligence is in the main controller with the native PCIe interface connection to the host, BiTMICRO’s solution also does not suffer from the latency issue of the multiple-controller solution. In fact, the main controller can also function as single-chip SSD controller without the flash channel expander chip. The main controller has the capability, if enabled, to interface directly to the flash devices.
Since flash channel expander chips support chaining, this dual-ASIC solution opens up the possibility of scaling disk capacity and flash channel bandwidth independent to the main controller. A common number of flash channels per SSD controller is 8 to 16. With just two levels of chaining of flash channel expanders, we can achieve 32 flash channels per SSD controller. The application of this solution is not limited to a single drive. It is being envisioned that 1 or 2 flash channel expander chips with an array of flash devices, by themselves, can function as a separate drive – an extremely cost effective, low-power drive.
An array of these “small” drives could then be connected as separate boards to the main controller, which, in itself, could also be on a separate pluggable board. Two main controllers could each be connected to all the “small” drives, thus providing high-availability. The capacity could be increased by adding more of these “small” drives and they could be easily replaced with new ones holding the latest flash devices, all without replacing the main controller.
The BiTMICRO dual-ASIC solution is the best of both controller options plus even more!
Writer: Federico Sambilay, ASIC Engineer